Isolation of adjacent semiconductor devices is an important structural consideration when manufacturing integrated circuits. Isolation is critical for improving integrated circuit yield and performance. In most cases, in order to improve device isolation, integrated circuit surface area increases or integrated circuit process complexity increases.
For example, most integrated circuits are manufactured using metal oxide semiconductor (MOS) field effect transistor (FET) technology. The most commonly used MOSFET technology for integrated circuit (IC) fabrication is known as complementary MOS (CMOS). CMOS devices, or other known IC devices, are conventionally isolated by field oxide which is usually formed as a thermally grown oxide layer. As semiconductor film thicknesses and lithographic features shrink, the field oxide isolation structures do not scale downward accordingly. Therefore, field oxide isolation structures and similar technologies, such as local oxidation of silicon (LOCOS), polysilicon buffered LOCOS (PBL), and the like, may not provide sufficient circuit density or sufficient isolation for future IC designs.
Trench or dielectric plug isolation is sometimes used to improve isolation between adjacent devices. Trench isolation or dielectric plug isolation increases process complexity and introduces etch damage into an integrated circuit substrate. Interface states and etch damage increase undesirable leakage currents within the integrated circuit. In addition, process integration of trench isolation results in gate oxide reliability problems and device defectivity problems.
In order to achieve further isolation, a modified field oxide approach is used wherein epitaxial growth is utilized to grow substrate material vertically and/or laterally over a field oxide region. The grown epitaxial regions are then used to form lateral transistors which are conventional (i.e. identical to conventional top-contacted bipolar and top-contacted MOS transistors). Although the method of epitaxially growing adjacent and/or over oxides improved isolation, the transistor devices which are formed within the grown epitaxial region have surface areas which are large due to electrical contacts methodologies and lithographically defined features, such as gate electrodes, source and drains, and contacts.
Another form of isolation is achieved via the use of silicon on insulator (SOI) technology or a similar technology, such as silicon on sapphire (SOS). Many different SOI processes and devices exist but most SOI processes result in a device-quality substrate material, such as single-crystalline silicon, entirely overlying a dielectric layer wherein the device-quality substrate material is not connected to the substrate. In another form, an SOI structure may be formed which has a source region, a drain region, and a channel region formed overlying a dielectric layer wherein only the channel region is connected to the substrate by a conductive plug region.
SOI transistors provide improved isolation over field oxide approaches and most SOI transistors have several advantages over planar substrate-formed transistors. Some of these advantages are the absence of latch-up in SOI, higher soft-error immunity and reduced parasitic capacitance. SOI transistors with no substrate or body contact suffer from a known and understood "kink effect", suffer from a known and understood "snap-back" phenomenon (which is similar to the "kink effect"), and have an undesirable parasitic bipolar transistor. SOI transistors with a substrate contact tend to have no "kink effect" or "snap-back" problems and may allow for adjustable threshold voltages and noise margins due to substrate biasing and the known and understood body effect.
Therefore, SOI transistors with a substrate contact have advantages and disadvantages, and SOI transistors without a substrate contact also have advantages and disadvantages. Neither SOI transistor is optimal in all cases and applications. In most cases, the most desirable SOI transistor is a thin-film SOI device which operates in a fully-depleted mode of operation. A thin-film SOI transistor operating in a fully-depleted mode of operation reduces "kink effect", has low electric fields, has a high transconductance, has excellent short channel behavior, and has a quasi-real subthreshold slope. SOI processing tends to be complex or unreliable. For example, separation by implantation of oxygen (SIMOX), which is used to form SOI devices, is a high temperature process and may produce substrate defects which degrade device performance.
Therefore, the need exists for an improved isolation structure and an improved method of isolation formation wherein the method is not complex. In addition, the structure should result in isolation which is superior to field oxide isolation, result in minimum device separation, and result in reduced device surface area. Furthermore, a flexible, dynamic, and easy to manufacture SOI device is desired for improved isolation and improved device performance.